Test modes in a microcontroller unit (MCU) provide controllability and observability of otherwise inaccessible address and data used by the MCU. Data and control information can be loaded and read from an MCU either serially or in parallel. Serial processing requires a minimum number of pins, but is quite slow. For example, it typically takes eight to ten clock cycles per byte when done serially.
Since test time has a material impact on the cost of an integrated circuit, these eight-to-ten cycles used for serial loading and reading of data and control information can be quite costly. A traditional solution has been to load and read data, address, and control information in parallel. Optimally, a sufficient number of pins to externalize the address bus, the data bus, and control information is used. For example, this may require 16 address pins, 8 data pins, and several control pins to control reading, writing, and other control functions. This solution has a serious disadvantage in that it significantly increases the number of pins utilized for the integrated circuit. Reducing pin count reduces packaging size and therefore packaging costs.
FIG. 1 is a block diagram illustrating a typical microcontroller unit (MCU) 20 as known in the prior art. The MCU 20 has a central processing unit (CPU) 22, memory 24, direct memory access unit (DMA) 26 communicating on a bi-directional internal bus 28. Also coupled to the bi-directional internal bus 28 are peripheral 32, peripheral 34, and peripheral 36. Peripheral 32 communicates external to the MCU 20 on pins 33. Peripheral 36 communicates on pin 37. Also coupled to the internal bus 28 is a test port 38 which communicates on test pins 39. In this example, peripheral 32 is shown connected to external pins 33, peripheral 36 is shown connected to peripheral pin 37 and test port 38 is shown connected to external test port pins 39. Examples of peripheral modules 32, 34, 36 are timers, serial peripheral interfaces (SPI), synchronous communications interfaces (SCI), A/D converters, PLLs, keyboards, and other auxiliary devices. The term peripheral here includes modules that are connected to external pins, and those, such as PLLs, that are not. Indeed, the term peripheral here should be taken to include any functional blocks included in an MCU 20 other than CPU 22 memory 24, DMA 26, or test ports 38. The CPU 22 and DMA 26 can be treated as peripherals for purposes of testing and hereinbelow. Typically, the CPU 22, the DMA 26, and potentially the test port 38 are bus masters of the bi-directional internal bus 28 whereas the memory 24, and the peripherals 32, 34, 36 are bus slaves. Typically, pins used for testing 39 cannot also be used for peripherals 33, 37.
One prior art solution to reducing pin count while maintaining parallel loading and reading of test information is a time multiplexing of address, data, and control information on a smaller number of pins. Indeed, a logical extension of this time multiplexing is a serial loading where everything is time multiplexed over a single serial port. This approach is a compromise approach and still has the problem of requiring at a minimum approximately eight pins. There is a trade-off of the number of pins used against test speed, with serial loading and reading at one end of the tradeoff and full parallel loading and reading at the other end of the tradeoff.
Referring back to FIG. 1, it should be noted that peripheral 32 is shown with four dedicated external pins 33 and peripheral 36 is shown with one external pin 37. As the number of peripherals 32, 34, 36 increases, as a result of larger and larger scale integration, the number of pins 33, 37 dedicated to peripherals 32, 36, increases accordingly. The number of pins 39 that can be thus dedicated to testing on a test port 38 correspondingly decreases in order to maintain low pin-count packages.
Another prior art solution is to utilize peripheral pins 33, 37 as test pins 39. One major problem with this solution is the loss of the ability to test the peripheral 32, 36 via its pins 33, 37 in test mode. This introduces serious reliability and verifiability problems.
It would thus be advantageous to be able to provide for parallel loading and reading of the MCU 20 in test mode, while maintaining the ability to test peripherals 32, 36 via their peripheral pins 33, 37, in a minimum pin-count integrated circuit.